1. Field of the Invention
This invention pertains to the architecture of an image processing system which serves as an intelligent high performance peripheral device in a digital imaging system. More specifically, the invention pertains to a bus structure, a timing and a protocol for use in such an image processing system. The bus structure provides an interconnection in which multiple array processors and memory modules can communicate simultaneously at a maximum transfer rate for a given number of bus lines and a given clock rate.
2. Description of the Prior Art
A variety of bus structures are well known in the prior art. Bus structures for real time video processing to date have a known number of shortcomings. To keep up with the demands of video rate information transfer, a bus architecture must overcome a number of classical drawbacks. One common drawback is the inability of the bus structure to achieve maximum throughput because of the inherent time delay between initiation of a memory read cycle and the availability of valid data at the memory output. Other drawbacks are also known in the art. Occasionally very complex process arbitration is needed to satisfy conflicting demands for a bus. Furthermore, there is often dead time inherent in the write-to-read transition. Many classic designs require very fast memory which in turn increases the cost of a system. Interface structures in the prior art have become quite complex because of the timing required for data address and control signals. The architecture of the bus structure of the present invention is designed to eliminate the various transmission bottlenecks which have occurred in prior art bus designs.